1. Field of the Invention
The present invention relates to the field of focal plane arrays, and more particularly, to the field of cryogenic focal plane arrays.
2. Background Information
Many optical surveillance systems employ focal plane arrays to sense image information. One important class of focal plane arrays are infrared sensing arrays. Such arrays are useful for image detection and motion sensing.
All objects, including the components of a focal plane array system, give off infrared radiation whose intensity is proportional to their temperature. In order to maximize system sensitivity and minimize noise, thereby maximizing signal-to-noise ratio, it is common to cool infrared sensing focal plane arrays to cryogenic temperatures in order to minimize system-induced noise in detected images and to prevent system component emissions from swamping desired low intensity images. By cryogenic temperatures, we mean temperatures of less than about 210.degree. K. (-63.degree. C.), with the preferred operating temperatures for such systems typically being less than about 100.degree. K.
Different semiconductor materials are inherently sensitive to different portions of the electromagnetic spectrum as a result of their internal energy band structure. Indium antimonide (InSb) and mercury cadmium telluride (HgCdTe) are well known materials which are suitable for the detection of infrared radiation. InSb is fairly extensively used in infrared sensors because of the wavelengths to which it is sensitive and because of the ability to process it with reasonable yields. One of the characteristics of InSb is that its structure is subject to temperature-induced degradation. It is considered desirable to prevent the exposure of an InSb infrared photodetector to temperatures in excess of about 150.degree. C., since the closer to 200.degree. C. and the longer the time for which the photodetector is exposed to such a temperature, the greater is the deterioration of an infrared photosensor in the form of increased noise and reduced detectivity. Where high sensitivity is desired, such noise is a particular problem and, therefore, high temperature exposure is studiously avoided or prevented. Mercury cadmium telluride is suitable for detection of infrared radiation over a wider band of frequencies or wavelengths than is InSb, but HgCdTe is more difficult to process and substantially more temperature sensitive than InSb. Consequently, it is not as widely used as InSb.
While InSb and HgCdTe are suitable for infrared detection, they are not suitable for the formation of integrated circuits or other electronics suitable for processing of image information which is collected by suitably processed imagers. Consequently, it is the standard practice in the infrared sensing art to connect an infrared sensor such as InSb or HgCdTe to silicon-based integrated circuits for processing of the image information produced by the infrared sensor
The image information provided by the InSb or HgCdTe infrared photosensor is normally in the form of a low amplitude current or small packets of charge.
Because of the incompatibility between the infrared sensor material and the silicon of the readout system, the image sensor and the readout system are normally separately fabricated on different substrates (respectively, InSb or HgCdTe and silicon). In a system, the photodetector or focal plane array and the readout circuits are normally mounted on a common substrate or circuit board and interconnected by wire bonds to form a sensor hybrid. Such wire bonds are also referred to as flying leads because they are secured only at their opposite ends where they are bonded to the photodetector and the integrated circuit, respectively. Where particularly fine resolution is desired, even the relatively thin flying lead and its minimum lead-to-lead spacing become a limitation on sensor array density. This is because even with state-of-the-art wire bonding equipment, wire bonds cannot be made closer together than about 2.5 mils, center-to-center, and because of the need to allow sufficient space between adjacent wire bonds to ensure against the creation of intermittent or permanent short circuits during normal use as a result of vibration or other phenomena. Such fine, closely spaced wire bond connections are easily damaged by accidental contact. Consequently, once wired, such focal plane array sensor hybrids must be handled extremely carefully to prevent damage to them. A further and significant problem in applications where the system is subjected to significant vibration, is the tendency of the flying leads to vibrate which results in additional noise in the system (known as microphonics) and which can lead to unintentional short circuits among adjacent wires.
Initially, focal plane array yield with InSb was a significant problem even with linear arrays, however, the yield of such linear arrays is now high enough that the testing of such arrays no longer presents a problem.
In contrast, with two dimensional InSb arrays, there is still a significant yield problem in the form of excessive numbers of so-called dead pixels or cells which provide no output, provide a constant output or provide a very noisy output. A more significant problem where tight tolerance is required on noise specifications, is the difficulty of determining the noise characteristics of individual cells of a focal plane array prior to connection of that focal plane array in a system. During wafer test of a two dimensional focal plane array, it is possible to determine whether or not entire rows or columns of cells are dead or inactive. However, it is impossible to determine the presence of individual (i.e. isolated or randomly positioned) bad pixels or the degree of noise generation or noise susceptibility of individual pixels.
Because of the hybrid nature of a focal plane array sensor hybrid in which the focal plane array itself and its readout system are fabricated from different semiconductor materials, it is impossible to fully test a two dimensional focal plane array prior to connecting it to its silicon readout circuitry. All present connection technologies for connecting an infrared focal plane array chip to silicon readout circuitry are non-repairable in the sense that once wire bonds have been connected from the focal plane array chip to a silicon readout chip, that focal plane array chip and those silicon readout chips cannot be rewired as by removing those wire bonds and rewiring any of those chips with new wirebonds in a production environment. However, in a laboratory situation, we have reworked wirebonded InSb and silicon chips with some success. However, this is risky, has a low probability of success and is not considered acceptable for production systems. As a consequence, when a focal plane array is connected to a readout system (which is normally a multiplexer), it becomes committed to use with those readout chips. In the event that the entire combination of the focal plane array and the readout chips does not meet specifications, the entire combination must be discarded. At present, this is an expensive proposition both because of the initial cost of the focal plane array and the silicon readout circuit chips and because of the further cost associated with the substrate on which the focal plane array and the silicon circuits are mounted for interconnection among themselves and to the remainder of the system for ultimate system use. It is only when the readout multiplexers have been connected to the infrared sensor array that the presence of individual bad pixels can be absolutely determined.
The hybrid board on which the focal plane array and the readout multiplexing circuits are mounted has a much larger area than the focal plane array itself. Because of the wire bond techniques used to connect the focal plane array to the readout multiplexers, these chips must always be disposed in a common plane. As a result, the dewar in which the focal plane array sensor hybrid is mounted must be substantially larger than it would have to be if only the focal plane array were mounted in the dewar. In size and weight sensitive systems, especially such systems intended for airborne or space application, the large dewar size is a substantial drawback both because of its own size and weight and because of the increased heat load which it places on the cooling system. This, in turn, requires a large cooling system than would be required if a smaller dewar could be used. Consequently, any advance in focal plane array sensor hybrid construction which enables the area occupied by a focal plane array sensor hybrid to be reduced, offers a multiplication of advantages in the form of system size and weight reduction as compared to prior art systems.
After assembly into the overall focal plane array sensor hybrid, the entire hybrid is mounted in a cryogenic dewar and cooled to a temperature in the vicinity of 78 to 82.degree. K. and subjected to a test which is known as the "zero degree field of view" test. In this test, external infrared illumination is excluded from the focal plane array. The focal plane array is then read out using the silicon multiplexer readout circuitry to detect the presence of leaky or noisy pixels in the array. For a 128 by 128 cell array (which has 16,384 pixels), a specification such as a maximum of 0.5% dead pixels limits the array to only 82 dead pixels in the entire array. Where noisy or leaky pixels are considered dead pixels, this puts stringent requirements on the focal plane array. More significantly, it is this small percentage which makes it necessary to connect the focal plane array to its readout multiplex circuits prior to performing this test. Assuming that the focal plane array sensor hybrid passes this zero degree field of view test, additional tests such as flood illumination combined with cell-to-cell uniformity determinations are performed as part of the acceptance test for such a focal plane array.
Because of the inability to rework the connections among the focal plane array and its silicon readout circuits, a complete focal plane array sensor hybrid which fails its acceptance tests must be scrapped even if all of its components except one is acceptable. Discarding such a system is expensive.
An additional cost associated with this assembly technique and test system is the fact that the focal plane array sensor hybrids must be individually mounted and cooled for testing with the result that substantial expense is involved in the testing alone.
Consequently, there is a need for an improved test and connection structure for such focal plane array sensor hybrids which will enable effective testing and repair and lead to substantial reductions in testing costs.
A high density interconnect (HDI) structure or system which has been developed by General Electric Company offers many advantages in the compact assembly of electronic systems. For example, an electronic system such as a micro computer which incorporates 30-50 chips can be fully assembled and interconnected on a single substrate which is 2 inch long by 2 inch wide by 0.050 inch thick. Even more important, this interconnect structure can be disassembled for repair or replacement of a faulty component and then reassembled without significant risk to the good components incorporated within the system. This is particularly important where as many as 50 chips having a cost of as much as $2,000.00, each, may be incorporated in a single system on one substrate. This repairability is a substantial advance over prior connection systems in which reworking the system to replace damaged components was either impossible or involved substantial risk to the good components.
Briefly, in this high density interconnect structure, a ceramic substrate such as alumina which may be 100 mils thick and of appropriate size and strength for the overall system, is provided. This size is typically less than 2 inches square. Once the position of the various chips has been specified, individual cavities or one large cavity having appropriate depth at the intended locations of differing chips, is prepared. This may be done by starting with a bare substrate having a uniform thickness and the desired size. Conventional or laser milling may be used to form the cavities in which the various chips and other components will be positioned. For many systems where it is desired to place chips edge-to-edge, a single large cavity is satisfactory. That large cavity may typically have a uniform depth where the semiconductor chips have a substantially uniform thickness. Where a particularly thick or a particularly thin component will be placed, the cavity bottom may be made respectively deeper or shallower to place the upper surface of the corresponding component in substantially the same plane as the upper surface of the rest of the components and the portion of the substrate which surrounds the cavity. The bottom of the cavity is then provided with a thermoplastic adhesive layer which may preferably be polyetherimide resin available under the trade name ULTEM.RTM. from the General Electric Company. The various components are then placed in their desired locations within the cavity, the entire structure is heated to the softening point of the ULTEM.RTM. polyetherimide (in the vicinity of 217.degree. C. to 235.degree. C. depending on the formulation used) and then cooled to thermoplastically bond the individual components to the substrate. Thereafter, a polyimide film which may be Kapton.RTM. polyimide, available from E.I. du Pont de Nemours Company, which is .apprxeq.0.0005-0.003 inch (.apprxeq.12.5-75 microns) thick is pretreated to promote adhesion and coated on one side with the ULTEM.RTM. polyetherimide resin or another thermoplastic and laminated across the top of the chips, any other components and the substrate with the ULTEM.RTM. resin serving as a thermoplastic adhesive to hold the Kapton.RTM. in place. Thereafter, via holes are laser drilled in the Kapton.RTM. and ULTEM.RTM. layers in alignment with the contact pads on the electronic components to which it is desired to make contact. A metallization layer which is deposited over the Kapton.RTM. layer extends into the via holes and makes electrical contact to the contact pads disposed thereunder. This metallization layer may be patterned to form individual conductors during the process of depositing it or may be deposited as a continuous layer and then patterned using photoresist and etching. The photoresist is preferably exposed using a scanned laser to provide an accurately aligned conductor pattern at the end of the process.
Additional dielectric and metallization layers are provided as required in order to provide all of the desired electrical connections among the chips. Any misposition of the individual electronic components and their contact pads is compensated for by an adaptive laser lithography system which is the subject of some of the Patents and Applications which are listed hereinafter.
In this manner, the entire interconnect structure can be fabricated from start to finish (after definition of the required conductor patterns and receipt of the electronic components) in as little as .apprxeq.8-12 hours.
This high density interconnect structure provides many advantages. Included among these are the lightest weight and smallest volume packaging of such an electronic system presently available. A further, and possibly more significant advantage of this high density interconnect structure, is the short time required to design and fabricate a system using this high density interconnect structure. Prior art processes require he prepackaging of each semiconductor chip, e design of a multilayer circuit board to interconnect the various packaged chips, and so forth. Multilayer circuit boards are expensive and require substantial lead time for their fabrication. In contrast, the only thing which must be specially pre-fabricated for the HDI system is the substrate on which the individual semiconductor chips will be mounted. This substrate is a standard stock item, other than the requirement that the substrate have appropriate cavities therein for the placement of the semiconductor chips so that the interconnect surface of the various chips and the substrate will be in a single plane. In the HDI process, the required cavities may be formed in an already fired ceramic substrate by conventional or laser milling. This milling process is straightforward and fairly rapid with the result that once a desired configuration for the substrate has been established, a corresponding physical substrate can be made ready for the mounting of the semiconductor chips in as little as 1 day and typically 4 hours for small quantities as are suitable for research or prototype systems to confirm the design prior to quantity production.
The process of designing an interconnection pattern for interconnecting all of the chips and components of an electronic system on a single high density interconnect substrate normally takes somewhere between one week and five weeks. Once that interconnect structure has been defined, assembly of the system on the substrate may begin. First, the chips are mounted on the substrate and the overlay structure is built-up on top of the chips and substrate, one layer at a time. Typically, the entire process can be finished in one day and in the event of a high priority rush, could be completed in four hours. Consequently, this high density interconnect structure not only results in a substantially lighter weight and more compact package for an electronic system, but enables a prototype of the system to be fabricated and tested in a much shorter time than is required with other packaging techniques.
This high density interconnect structure, methods of fabricating it and tools for fabricating it are disclosed in U.S. Pat. No. 4,783,695, entitled "Multichip Integrated Circuit Packaging Configuration and Method", by C. W. Eichelberger, et al.; U.S. Pat. No. 4,835,704, entitled "Adaptive Lithography System to Provide High Density Interconnect" by C. W. Eichelberger, et al.; U.S. Pat. No. 4,714,516, entitled "Method to Produce Via Holes in Polymer Dielectrics for Multiple Electronic Circuit Chip Packaging" by C. W. Eichelberger, et al.; U.S. Pat. No. 4,780,177, entitled "Excimer Laser Patterning of a Novel Resist" by R. J. Wojnarowski et al.; U.S. patent application Ser. No. 249,927, filed Sep. 27, 1988, entitled "Method and Apparatus for Removing Components Bonded to a Substrate" by R. J. Wojnarowski, et al.; U.S. Pat. No. 4,894,115 issued Jan. 16, 1990, entitled "Laser Beam Scanning Method for Forming Via Holes in Polymer Materials" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 312,798, filed Feb. 21, 1989, entitled "High Density Interconnect Thermoplastic Die Attach Material and Solvent Die Attachment Processing" by R. J. Wojnarowski, et al.; U.S. Pat. No. 4,878,991, issued Nov. 7, 1989, entitled "Simplified Method for Repair of High Density Interconnect Circuits" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 305,314, filed Feb. 3, 1989, entitled "Fabrication Process and Integrated Circuit Test Structure" by H. S. Cole, et al.; U.S. patent application Ser. No. 250,010, filed Sep. 27, 1988, entitled "High Density Interconnect With High Volumetric Efficiency" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 329,478, filed Mar. 28, 1989, entitled "Die Attachment Method for Use in High Density Interconnected Assemblies" by R. J. Wojnarowski, et al.; U.S. Pat. No. 4,960,613, issued Oct. 2, 1990 entitled "Laser Interconnect Process" by H. S. Cole, et al.; U.S. Pat. No. 4,884,122, issued Nov. 28, 1989, entitled "Method and Configuration for Testing Electronic Circuits and Integrated Circuit Chips Using a Removable Overlay Layer" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 233,965, filed Aug. 18, 1988, entitled "Direct Deposition of Metal Patterns for Use in Integrated Circuit Devices" by Y. S. Liu, et al.; U.S. Pat. No. 4,882,200 issued Nov. 21, 1989, entitled "Method for Photopatterning Metallization Via UV Laser Ablation of the Activator" by Y. S. Liu, et al.; U.S. patent application Ser. No. 237,685, filed Aug. 25, 1988, entitled "Direct Writing of Refractory Metal Lines for Use in Integrated Circuit Devices" by Y. S. Liu, et al.; U.S. Pat. No. 4,933,042, issued Jun. 12, 1990, entitled "Method and Apparatus for Packaging Integrated Circuit Chips Employing a Polymer Film Overlay Layer" by C. W. Eichelberger, et al.; U.S. Pat. No. 4,897,153 issued Jan. 30, 1990 entitled "Method of Processing Siloxane-Polyimides for Electronic Packaging Applications" by H. S. Cole, et al.; U.S. patent application 289,944, filed Dec. 27, 1988, entitled "Selective Electrolytic Deposition on Conductive and Non-Conductive Substrates" by Y. S. Liu, et al.; U.S. patent application Ser. No. 312,536, filed Feb. 17, 1989, entitled "Method of Bonding a Thermoset Film to a Thermoplastic Material to Form a Bondable Laminate" by R. J. Wojnarowski; U.S. patent application Ser. No. 363,646, filed Jun. 8, 1989, entitled "Integrated Circuit Packaging Configuration for Rapid Customized Design and Unique Test Capability" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 07/459,844, filed Jan. 2, 1990, entitled "Area-Selective Metallization Process" by H. S. Cole, et al.; U.S. patent application Ser. No. 07/457,023, filed Dec. 26, 1989, entitled "Locally Orientation Specific Routing System" by T. R. Haller, et al.; U.S. patent application Ser. No. 456,421, filed Dec. 26, 1989, entitled "Laser Ablatable Polymer Dielectrics and Methods" by H. S. Cole, et al.; U.S. patent application Ser. No. 454,546, filed Dec. 21, 1989, entitled "Hermetic High Density Interconnected Electronic System" by W. P. Kornrumpf, et al.; U.S. patent application Ser. No. 07/457,127, filed Dec. 26, 1989, entitled "Enhanced Fluorescence Polymers and Interconnect Structures Using Them" by H. S. Cole, et al.; and U.S. patent application Ser. No. 454,545, filed Dec. 21, 1989, entitled "An Epoxy/Polyimide Copolymer Blend Dielectric and Layered Circuits Incorporating It" by C. W. Eichelberger, et al. Each of these Patents and Patent Applications is incorporated herein by reference.
This high density interconnect system has been developed for and applied to the military digital system temperature range of -55.degree. C. to +150.degree. C. However, its suitability for use at cryogenic temperatures such as 77.degree. K. (the boiling point of liquid nitrogen) have not been established. Concerns associated with possible application of this system to such temperatures include the integrity of the various dielectric layers, both at these temperatures and during transitions from room temperature to these temperatures and the effects of thermal contraction of the various dielectric layers and conductors during cooling from room temperature to these cryogenic temperatures.
Another problem with this high density interconnect structure is the fact that it applies its dielectric layer over the entire system it is to interconnect and the polyimide and polyetherimide materials which serve as its dielectric material exhibit substantial absorbence of the infrared frequencies of interest in InSb and HdCdTe infrared sensing systems. Even the 0.5 to 3 mil thick layers of these materials which are employed as the initial dielectric layer in this high density interconnect structure can attenuate infrared signals of interest in focal plane array work by as much as 30% or more.
A further problem with respect to use of this high density interconnect structure with infrared focal plane arrays is that the 220.degree. C. processing temperatures for this high density interconnect structure using the ULTEM polyetherimide resin as the thermoplastic adhesive is much too high for use with InSb and HgCdTe focal plane array chips.
The above-identified related application Ser. No. 07/504,821 discloses the removal of the dielectric layers of the high density interconnect structure over dielectric-constant-sensitive portions of a microwave circuit to minimize high density interconnect structure/component interactions in a microwave system.
Consequently, there is a need for a more accommodating connection system for connecting focal plane arrays to their readout circuits.